library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity single_voter_one_bit is
	port (
		input0 : in std_logic;
		input1 : in std_logic;
		input2 : in std_logic;
		input3 : in std_logic;
		sel0 : in std_logic_vector (1 downto 0);
		sel1 : in std_logic_vector (1 downto 0);
		sel2 : in std_logic_vector (1 downto 0);
		correct_output : out std_logic;
		fault0 : out std_logic;
		fault1 : out std_logic;
		fault2 : out std_logic
	);
	
end entity;

architecture behavioral of single_voter_one_bit is

signal aux_correct_output :  std_logic;
signal aux_in0 :  std_logic;
signal aux_in1 :  std_logic;
signal aux_in2 :  std_logic;

component mux_4_1_one_bit is
	port (
		in0 : in std_logic;
		in1 : in std_logic;
		in2 : in std_logic;
		in3 : in std_logic;
		sel : in std_logic_vector (1 downto 0);
		output : out std_logic
	);
end component;

begin


multiplexer0 : mux_4_1_one_bit
	port map(
		in0 => input0,
		in1 => input1,
		in2 => input2,
		in3 => input3,
		sel => sel0,
		output => aux_in0
	);
multiplexer1 : mux_4_1_one_bit
	port map(
		in0 => input0,
		in1 => input1,
		in2 => input2,
		in3 => input3,
		sel => sel1,
		output => aux_in1
	);
multiplexer2 : mux_4_1_one_bit
	port map(
		in0 => input0,
		in1 => input1,
		in2 => input2,
		in3 => input3,
		sel => sel2,
		output => aux_in2
	);
	
	P1 : process(aux_in0, aux_in1, aux_in2)
	begin
		if aux_in0 = aux_in1 then
			if aux_in0 = aux_in2 then	--all correct
				fault0 <= '0';
				fault1 <= '0';
				fault2 <= '0';
				aux_correct_output <= aux_in0;
			else	--in0=in1 and in0!=in2 => in2 is wrong
				fault0 <= '0';
				fault1 <= '0';
				fault2 <= '1';
				aux_correct_output <= aux_in0;
			end if;
		else
			if aux_in1 = aux_in2 then	--in0 is wrong
				fault0 <= '1';
				fault1 <= '0';
				fault2 <= '0';
				aux_correct_output <= aux_in1;
			else
				if aux_in0 = aux_in2 then	--in1 is wrong
					fault0 <= '0';
					fault1 <= '1';
					fault2 <= '0';
					aux_correct_output <= aux_in0;
				else	--more than one fault
					fault0 <= '1';
					fault1 <= '1';
					fault2 <= '1';
					aux_correct_output <= '0';
				end if;
			end if;
		end if;
	end process;
	correct_output <= aux_correct_output;
end behavioral;
			